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2001 data sheet description the pd780833y is a member of the pd780833y subseries of the 78k/0 series, and incorporates a rich lineup of peripheral hardware, including a j1850 (class2) bus controller, a/d converter, timer, serial interface, and interrupt controller. a flash memory version, the pd78f0833y, and various development tools are also available. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. pd780833y subseries user? manual: u13892e 78k/0 series user? manual instructions: u12326e features on-chip j1850 (class2) bus controller on-chip rom and ram item program memory data memory package internal rom internal high- internal expansion part number speed ram ram pd780833y 60 kb 1024 bytes 2048 bytes 80-pin plastic qfp (14 14) minimum instruction execution time can be changed from high speed (0.48 s) to low speed (7.68 s) i/o ports: 65 (n-ch open-drain: 3, ttl input/cmos output: 8) 8-bit resolution a/d converter: 8 channels 2 serial interface: 4 channels timer: 7 channels power supply voltage: v dd = 4.5 to 5.5 v applications car audios, etc. 8-bit single-chip microcontroller document no. u15012ej1v0ds00 (1st edition) date published january 2001 n cp(k) printed in japan mos integrated circuit pd780833y the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
pd780833y data sheet u15012ej1v0ds 2 ordering information part number package pd780833ygc- -8bt 80-pin plastic qfp (14 14) remark indicates rom code suffix.
pd780833y data sheet u15012ej1v0ds 3 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78054 with added iebus tm controller. reduced emi noise. pd78054 with enhanced serial i/o pd78078y with enhanced serial i/o and limited functions 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with added uart and d/a converter and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with increased ram capacity pd780024a with enhanced a/d converter on-chip inverter controller and uart. reduced emi noise. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and increased rom, ram capacity emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin 100-pin 100-pin products in mass production products under development y subseries products support i 2 c bus. pd78054 with added timer and enhanced external interface romless version of the pd78078 100-pin 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780824 for automobile meter driver. on-chip d-can controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin pd780701y on-chip d-can/iebus controller 80-pin pd780833y on-chip controller compliant with j1850 (class2) pd780948 on-chip d-can controller 64-pin pd780078 pd780078y pd780034a with added timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pd780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with added n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for driving vfd. display output total: 34 120-pin pd780308 with enhanced display function and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display function and timer. segment signal output: 32 pins max. pd780308 with enhanced display function and timer. segment signal output: 24 pins max. pd780338
pd780833y data sheet u15012ej1v0ds 4 the major functional differences among the subseries are shown below. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a min. value expansion control pd78078y 48 k to 60 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch, 88 1.8 v pd78070ay i 2 c: 1 ch) 61 2.7 v pd780018ay 48 k to 60 k 3 ch (i 2 c: 1 ch) 88 pd780058y 24 k to 60 k 2 ch 2 ch 3 ch (time division 68 1.8 v uart: 1 ch, i 2 c: 1 ch) pd78058fy 48 k to 60 k 3 ch (uart: 1 ch, 69 2.7 v pd78054y 16 k to 60 k i 2 c: 1 ch) 2.0 v pd780078y 48 k to 60 k 2 ch 8 ch 4 ch (uart: 2 ch, 52 1.8 v i 2 c: 1 ch) pd780034ay 8 k to 32 k 1 ch 3 ch (uart: 1 ch, 51 pd780024ay 8 ch i 2 c: 1 ch) pd78018fy 8 k to 60 k 2 ch (i 2 c: 1 ch) 53 lcd pd780308y 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 3 ch (time division 57 2.0 v drive uart: 1 ch, i 2 c: 1 ch) pd78064y 16 k to 32 k 2 ch (uart: 1 ch, i 2 c: 1 ch) pd780701y 60 k 3 ch 2 ch 1 ch 1 ch 16 ch 4 ch (uart: 1 ch, 67 3.5 v pd780833y i 2 c: 1 ch) 65 4.5 v bus interface supported
pd780833y data sheet u15012ej1v0ds 5 function overview item pd780833y internal rom 60 kb memory high-speed ram 1024 bytes expansion ram 2048 bytes memory space 64 kb general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time on-chip variable function of minimum instruction execution time 0.48 s/0.96 s/1.92 s/3.84 s/7.68 s (@4.19 mhz operation) instruction set 16-bit operation multiply/divide (8 bits 8 bits,16 bits 8 bits) bit manipulation (set, reset, test, boolean operation) bcd adjust, etc. i/o ports total: 65 cmos input: 54 ttl input/cmos output: 8 n-ch open-drain i/o: 3 a/d converter 8-bit resolution 8 channels 2 serial interface 3-wire serial i/o mode: 2 channels uart mode: 1 channel i 2 c bus mode: 1 channel timer 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 3 channels watch timer: 1 channel watchdog timer: 1 channel timer outputs 5 (8-bit pwm output capable: 3) clock output 32.8 khz, 65.5 khz, 130.9 khz, 261.9 khz, 523.6 khz, 1.05 mhz, 2.10 mhz, 4.19 mhz (@4.19 mhz operation with system clock) bus controller bus interface compliant with j1850 (class2) vectored maskable internal: 19, external: 9 interrupt non-maskable internal: 1 source software 1 power supply voltage v dd = 4.5 to 5.5 v operating ambient temperature t a = 40 to +85 c package 80-pin plastic qfp (14 14)
pd780833y data sheet u15012ej1v0ds 6 contents 1. pin configuration (top view) ........................................................................................... 7 2. block diagram ......................................................................................................................... 9 3. pin functions ............................................................................................................................ 10 3.1 port pins ............................................................................................................................... .. 10 3.2 non-port pins ........................................................................................................................ 11 3.3 pin i/o circuits and recommended connection of unused pins .................................. 13 4. memory space ........................................................................................................................... 15 5. peripheral hardware function features ............................................................... 16 5.1 ports ....................................................................................................................... ................. 16 5.2 clock generator .................................................................................................................... 17 5.3 timer ............................................................................................................................... ........ 18 5.4 clock output controller ....................................................................................................... 22 5.5 a/d converter ........................................................................................................................ 23 5.6 serial interface ...................................................................................................................... 24 5.7 j1850 (class2) bus controller .......................................................................................... 27 6. interrupt functions ............................................................................................................. 28 7. standby functions ................................................................................................................. 32 8. reset functions ...................................................................................................................... 32 9. instruction set ....................................................................................................................... 33 10. electrical specifications .................................................................................................. 35 11. package drawing .................................................................................................................... 49 12. recommended soldering conditions ........................................................................... 50 appendix a. development tools ........................................................................................... 51 appendix b. related documents .......................................................................................... 56
pd780833y data sheet u15012ej1v0ds 7 1. pin configuration (top view) 80-pin plastic qfp (14 14) pd780833ygc- -8bt cautions 1. connect the ic (internally connected) pin directly to v ss0 or v ss1 . 2. connect the av dd0 pin to v dd0 . 3. connect the av ss0 and av ss1 pins to v ss0 . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p70/pcl p71/sda0 p72/scl0 p73/to01 p74/ti001 p75/ti011 p00/intp0 p01/intp1 p02/intp2 p03/intp3 av ref1 p80/ani01 p81/ani11 p82/ani21 p83/ani31 p84/ani41 p85/ani51 p86/ani61 p87/ani71 av ss1 p66 p65 p64 p27/ti51/to51 p26/asck0/ti52/to52 p25/txd0 p24/rxd0 p23/ti50/to50 p07/intp7 p06/intp6 p05/intp5 p04/intp4 p22/sck31 p21/so31 p20/si31 p57 p56 p55 p54 p53 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 av ss0 p97/ani70 p96/ani60 p95/ani50 p94/ani40 p93/ani30 p92/ani20 p91/ani10 p90/ani00 av ref0 av dd0 v dd1 v ss1 x1 x2 ic reset c2tx c2rx p67 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p40 p41 p42 p43 p44 p45 p46 p47 p30/si30 p31/so30 p32/sck30 v dd0 v ss0 p33 p34/to00 p35/ti000 p36/ti010 p50 p51 p52 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
pd780833y data sheet u15012ej1v0ds 8 ani00 to ani70,: analog input ani01 to ani71 asck: asynchronous serial clock av dd0 : analog power supply av ref0 , av ref1 : analog reference voltage av ss0 , av ss1 : analog ground c2rx: class2 receive data c2tx: class2 transmit data ic: internally connected intp0 to intp7: external interrupt input p00 to p07: port 0 p20 to p27: port 2 p30 to p36: port 3 p40 to p47: port 4 p50 to p57: port 5 p64 to p67: port 6 p70 to p75: port 7 p80 to p87: port 8 p90 to p97: port 9 pcl: programmable clock rxd0: receive data reset: reset sck30, sck31: serial clock scl0: serial clock sda0: serial data si30, si31: serial input so30, so31: serial output ti000, ti010, ti001,: timer input ti011, ti50, ti51, ti52 to00, to01, to50,: timer output to51, to52 txd0: transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground x1, x2: crystal
pd780833y data sheet u15012ej1v0ds 9 2. block diagram 16-bit timer/ event counter 00 16-bit timer/ event counter 01 serial interface 30 serial interface 31 watchdog timer watch timer uart0 i 2 c bus j1850 bus i/f (class2) interrupt control clock output control a/d converter 00 a/d converter 01 to00/p34 ti000/p35 ti010/p36 to01/p73 ti001/p74 ti011/p75 8-bit timer/ event counter 50 8-bit timer/ event counter 51 ti50/to50/p23 ti51/to51/p27 8-bit timer/ event counter 52 ti52/to52/p26 si30/p30 so30/p31 sck30/p32 si31/p20 so31/p21 sck31/p22 rxd0/p24 txd0/p25 asck0/p26 av dd0 av ss0 av ref0 sda0/p71 scl0/p72 ani00/p90 to ani70/p97 av ss1 av ref1 c2rx pcl/p70 c2tx ani01/p80 to ani71/p87 intp0/p00 to intp7/p07 78k/0 cpu core rom internal expansion ram 2048 bytes internal high-speed ram 1024 bytes v dd0 v dd1 v ss0 v ss1 ic port 0 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 p00 to p07 p20 to p27 p30 to p36 p40 to p47 p50 to p57 p64 to p67 p70 to p75 p80 to p87 p90 to p97 system control reset x1 x2
pd780833y data sheet u15012ej1v0ds 10 3. pin functions 3.1 port pins (1/2) pin name i/o function after reset alternate function p00 to p07 i/o input intp0 to intp7 p20 i/o input si31 p21 so31 p22 sck31 p23 ti50/to50 p24 rxd0 p25 txd0 p26 asck0/ti52/to52 p27 ti51/to51 p30 i/o input si30 p31 so30 p32 sck30 p33 p34 to00 p35 ti000 p36 ti010 p40 to p47 i/o port 4 input 8-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. the interrupt request flag (krif) is set to 1 by falling edge detection. p50 to p57 i/o port 5 input 8-bit i/o port ttl level input/cmos output input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. p64 to p67 i/o input port 0 8-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. port 2 8-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. port 3 7-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. use of an on-chip pull-up resistor can be specified by means of software. port 6 4-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. n-ch open-drain i/o port leds can be driven directly.
pd780833y data sheet u15012ej1v0ds 11 pin name i/o function after reset alternate function intp0 to input external interrupt request input for which the valid edge (rising edge, input p00 to p07 intp7 falling edge, or both rising and falling edges) can be specified si30 input serial interface sio30 serial data input input p30 si31 serial interface sio31 serial data input p20 so30 output serial interface sio30 serial data output input p31 so31 serial interface sio31 serial data output p21 sda0 i/o serial interface iic0 serial data input/output input p71 sck30 i/o serial interface sio30 serial clock input/output input p32 sck31 serial interface sio31 serial clock input/output p22 scl0 serial interface iic0 serial clock input/output p72 rxd0 input serial data input for asynchronous serial interface input p24 txd0 output serial data output for asynchronous serial interface input p25 asck0 input serial clock input for asynchronous serial interface input p26/ti52/to52 ti000 input external count clock input to 16-bit timer/event counter 00 input p35 capture trigger input to capture register (cr000 and cr010) of 16-bit timer/event counter 00 ti010 capture trigger input to capture register (cr000) of 16-bit timer/ p36 event counter 00 ti001 external count clock input to 16-bit timer/event counter 01 p74 capture trigger input to capture register (cr001 and cr011) of 16-bit timer/event counter 01 ti011 capture trigger input to capture register (cr001) of 16-bit timer/ p75 event counter 01 ti50 external count clock input to 8-bit timer/event counter 50 p23/to50 ti51 external count clock input to 8-bit timer/event counter 51 p27/to51 ti52 external count clock input to 8-bit timer/event counter 52 p26/asck0/to52 pin name i/o function after reset alternate function p70 i/o input pcl p71 sda0 p72 scl0 p73 to01 p74 ti001 p75 ti011 p80 to p87 i/o input ani01 to ani71 p90 to p97 i/o input ani00 to ani70 3.2 non-port pins (1/2) 3.1 port pins (2/2) port 8 8-bit i/o port input/output can be specified in 1-bit units. port 9 8-bit i/o port input/output can be specified in 1-bit units. port 7 6-bit i/o port input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. n-ch open-drain i/o port use of an on-chip pull-up resistor can be specified by means of software.
pd780833y data sheet u15012ej1v0ds 12 pin name i/o function after reset alternate function to00 output 16-bit timer/event counter 00 output input p34 to01 16-bit timer/event counter 01 output p73 to50 8-bit timer/event counter 50 output p23/ti50 to51 8-bit timer/event counter 51 output p27/ti51 to52 8-bit timer/event counter 52 output p26/asck0/ti52 pcl output clock output input p70 ani00 to input a/d converter (ad00) analog input input p90 to p97 ani70 ani01 to a/d converter (ad01) analog input p80 to p87 ani71 av ref0 a/d converter (ad00) reference voltage input av ref1 a/d converter (ad01) analog power supply and reference voltage input av dd0 a/d converter (ad00) analog power supply av ss0 a/d converter (ad00) ground potential. set the same potential as that of v ss0 or v ss1 . av ss1 a/d converter (ad01) ground potential. set the same potential as that of v ss0 or v ss1 . c2rx input class2 data input c2tx output class2 data output reset input system reset input x1 input crystal connection for oscillation x2 v dd0 positive power supply for ports v dd1 positive power supply (except ports) v ss0 ground potential of ports v ss1 ground potential (except ports) ic internally connected. connect directly to v ss0 or v ss1 . 3.2 non-port pins (2/2)
pd780833y data sheet u15012ej1v0ds 13 3.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the i/o circuit configuration of each type, see figure 3-1. table 3-1. types of pin i/o circuits and recommended connection of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 to p07/intp7 8-c i/o input: independently connect to v ss0 via a resistor. output: leave open. p20/si31 input: independently connect to v dd0 or v ss0 via a resistor. p21/so31 5-h output: leave open. p22/sck31 8-c p23/ti50/to50 p24/rxd0 p25/txd0 5-h p26/asck0/ti52/to52 8-c p27/ti51/to51 p30/si30 p31/so30 5-h p32/sck30 8-c p33 13-p input: independently connect to v dd0 via a resistor. output: leave open. p34/to00 5-h input: independently connect to v dd0 or v ss0 via a resistor. p35/ti000 8-c output: leave open. p36/ti010 p40 to p47 5-h input: independently connect to v dd0 via a resistor. output: leave open. p50 to p57 5-t input: independently connect to v dd0 or v ss0 via a resistor. p64 to p67 5-h output: leave open. p70/pcl p71/sda0 13-r input: independently connect to v dd0 via a resistor. p72/scl0 output: leave open. p73/to01 5-h input: independently connect to v dd0 or v ss0 via a resistor. p74/ti001 8-c output: leave open. p75/ti011 p80/ani01 to p87/ani71 11-e p90/ani00 to p97/ani70 c2rx 2 input connect to v ss0 via a resistor. c2tx 3-b output leave open. reset 2 input av dd0 connect to v dd0 . av ref0 av ref1 av ss0 connect to v ss0 . av ss1 ic connect directly to v ss0 or v ss1 .
pd780833y data sheet u15012ej1v0ds 14 figure 3-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics in type 5-h type 3-b type 8-c type 5-t type 11-e data output disable p-ch in/out v dd0 n-ch p-ch v dd0 pull-up enable v ss0 data output disable p-ch in/out v dd0 n-ch input enable p-ch v dd0 pull-up enable v ss0 in/out output disable data v dd0 p-ch n-ch p-ch comparator av ss input enable v ref (threshold voltage) + n-ch v ss0 out data v dd0 p-ch n-ch v ss0 pull-up enable v dd0 p-ch in/out input enable output disable data v dd0 p-ch n-ch v ss0 ttl input type 13-r type 13-p data output disable in/out n-ch v ss0 data output disable in/out n-ch input enable v ss0
pd780833y data sheet u15012ej1v0ds 15 4. memory space figure 4-1 shows the memory map of the pd780833y. figure 4-1. memory map 0000h data memory space general-purpose registers 32 8 bits internal rom 61440 8 bits efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal expansion ram 2048 8 bits bfffh efffh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 8 bits special function registers (sfrs) 256 8 bits reserved fb00h faffh f800h f7ffh program memory space
pd780833y data sheet u15012ej1v0ds 16 5. peripheral hardware function features 5.1 ports the following 3 types of i/o ports are available. cmos i/o (ports 0, 2 to 4, 6 to 9 (excluding p33, p71, and p72)): 54 ttl input/cmos output (port 5): 8 n-channel open-drain i/o (p33, p71, p72): 3 total: 65 table 5-1. port functions name pin name function port 0 p00 to p07 i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. port 2 p20 to p27 i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. port 3 p30 to p32, i/o port. input/output can be specified in 1-bit units. p34 to p36 use of an on-chip pull-up resistor can be specified by means of software. p33 n-ch open-drain i/o port. input/output can be specified in 1-bit units. leds can be driven directly. port 4 p40 to p47 i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. the interrupt request flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 ttl-level input/cmos output port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. port 6 p64 to p67 i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by means of software. port 7 p70, i/o port. input/output can be specified in 1-bit units. p73 to p75 use of an on-chip pull-up resistor can be specified by means of software. port 8 p80 to p87 i/o port. input/output can be specified in 1-bit units. port 9 p90 to p97 i/o port. input/output can be specified in 1-bit units.
pd780833y data sheet u15012ej1v0ds 17 5.2 clock generator a system clock generator is incorporated. the minimum instruction execution time can be changed. 0.48 s/0.95 s/1.91 s/3.81 s/7.63 s (at 4.19 mhz operation with system clock) figure 5-1. block diagram of clock generator x1 x2 system clock oscillator f x prescaler f x 2 f x 2 2 f x 2 3 f x 2 4 prescaler clock to peripheral hardware cpu clock (f cpu ) standby controller 3 stop pcc2 pcc1 pcc0 processor clock control register (pcc) internal bus selector
pd780833y data sheet u15012ej1v0ds 18 5.3 timer seven timer channels are incorporated. 16-bit timer/event counter: 2 channels 8-bit timer/event counter: 3 channels watch timer: 1 channel watchdog timer: 1 channel table 5-2. operations of timer/event counter 16-bit timer/event 8-bit timer/event watch timer watchdog timer counter 00, 01 counter 50, 51, 52 operation interval timer 2 channels 3 channels 1 channel note 1 1 channel note 2 mode external event counter 2 channels 3 channels function timer outputs 2 3 pwm outputs 3 ppg outputs 2 pulse width measurement 4 inputs square-wave outputs 2 3 one-shot pulse outputs 2 interrupt sources 4321 notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer has the watchdog timer and interval timer functions. however, use the watchdog timer by selecting either the watchdog timer function or the interval timer function.
pd780833y data sheet u15012ej1v0ds 19 figure 5-2. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/p36 f x f x /2 2 f x /2 6 f x /2 3 ti000/p35 prescaler mode register 00 (prm00) 2 prm001 prm000 crc002 16-bit capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise eliminator crc002 crc001 crc000 inttm000 to00/p34 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 ospt0 ospe0 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit capture/compare register 000 (cr000) selector selector selector noise eliminator noise eliminator output controller figure 5-3. block diagram of 16-bit timer/event counter 01 internal bus capture/compare control register 01 (crc01) ti011/p75 f x f x /2 2 f x /2 6 f x /2 3 ti001/p74 prescaler mode register 01 (prm01) 2 prm011 prm010 crc012 16-bit capture/compare register 011 (cr011) match match 16-bit timer counter 01 (tm01) clear noise eliminator crc012 crc011 crc010 inttm001 to01/p73 inttm011 16-bit timer output control register 01 (toc01) 16-bit timer mode control register 01 (tmc01) internal bus tmc013 tmc012 tmc011 ovf01 ospt1 ospe1 toc014 lvs01 lvr01 toc011 toe01 selector 16-bit capture/compare register 001 (cr001) selector selector selector noise eliminator noise eliminator output controller
pd780833y data sheet u15012ej1v0ds 20 figure 5-4. block diagram of 8-bit timer/event counter 50 internal bus internal bus ti50/to50/p23 f x /2 f x /2 2 f x /2 3 f x /2 5 f x /2 7 f x /2 11 selector 8-bit compare register 50 (cr50) match 8-bit timer counter 50 (tm50) 3 selector mask circuit clear ovf tcl502 tcl501 tcl500 timer clock select register 50 (tcl50) 8-bit timer mode control register 50 (tmc50) tce50 tmc506 tmc504 lvs50 lvr50 tmc501 toe50 s r inv s q r selector inttm50 selector to50/ti50/p23 level inversion figure 5-5. block diagram of 8-bit timer/event counter 51 internal bus internal bus ti51/to51/p27 f x /2 f x /2 2 f x /2 5 f x /2 7 f x /2 9 f x /2 11 selector 8-bit compare register 51 (cr51) match 8-bit timer counter 51 (tm51) 3 selector mask circuit clear ovf tcl512 tcl511 tcl510 timer clock select register 51 (tcl51) 8-bit timer mode control register 51 (tmc51) tce51 tmc516 tmc514 lvs51 lvr51 tmc511 toe51 s r inv s q r selector inttm51 selector to51/ti51/p27 level inversion
pd780833y data sheet u15012ej1v0ds 21 figure 5-6. block diagram of 8-bit timer/event counter 52 internal bus internal bus ti52/to52/asck0/p26 f x /2 f x /2 3 f x /2 4 f x /2 6 f x /2 8 f x /2 10 selector 8-bit compare register 52 (cr52) match 8-bit timer counter 52 (tm52) 3 selector mask circuit clear ovf tcl522 tcl521 tcl520 timer clock select register 52 (tcl52) 8-bit timer mode control register 52 (tmc52) tce52 tmc526 tmc524 lvs52 lvr52 tmc521 toe52 s r inv s q r selector inttm52 selector to52/ti52/asck0/p26 level inversion figure 5-7. block diagram of watch timer f x /2 6 f x /2 7 f w 11-bit prescaler clear clear intwtn0 intwtni0 5-bit prescaler selector selector selector selector watch timer operation mode register 0 (wtnm0) internal bus wtnm07 wtnm06 wtnm05 3 wtnm04 wtnm03 wtnm02 wtnm01 wtnm00 f w 2 5 f w 2 4 f w 2 6 f w 2 7 f w 2 8 f w 2 10 f w 2 11 f w 2 9
pd780833y data sheet u15012ej1v0ds 22 figure 5-8. block diagram of watchdog timer 5.4 clock output controller a clock output/buzzer output controller (cku) is incorporated. clocks with the following variation of frequency can be output as clock output. 32.8 khz/65.6 khz/131 khz/262 khz/524 khz/1.05 mhz/2.10 mhz/4.19 mhz (at 4.19 mhz operation with system clock) figure 5-9. block diagram of clock output controller 8 3 clock controller cloe pcl/p70 internal bus selector cloe ccs2 ccs1 ccs0 clock output select register (cks) prescaler f x to f x /2 7 f x f x /2 8 run clock input controller intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 run wdtm4 internal bus division circuit divided clock selector output controller division mode selector wdtm3 oscillation stabilization time select register (osts) watchdog timer clock select register (wdcs) watchdog timer mode register (wdtm)
pd780833y data sheet u15012ej1v0ds 23 5.5 a/d converter two a/d converters of 8-bit resolution 8 channels (ad00 and ad01) are incorporated. an a/d conversion operation can only be started by software. figure 5-10. block diagram of a/d converter (ad00) ani01/p80 ani11/p81 ani21/p82 ani31/p83 ani41/p84 ani51/p85 ani61/p86 ani71/p87 sample & hold circuit voltage comparator series resistor string successive approximation register (sar) 3 a/d conversion result register 01 (adcr01) av ref1 (alternative to analog power supply) av ss1 intad01 a/d converter mode register 01 (adm01) analog input channel specification register 01 (ads01) internal bus ads012 ads011 ads010 selector tap selector adcs01 fr021 fr011 fr001 figure 5-11. block diagram of a/d converter (ad01) ani00/p90 ani10/p91 ani20/p92 ani30/p93 ani40/p94 ani50/p95 ani60/p96 ani70/p97 sample & hold circuit voltage comparator series resistor string successive approximation register (sar) 3 a/d conversion result register 00 (adcr00) av dd0 av ref0 av ss0 intad00 a/d converter mode register 00 (adm00) analog input channel specification register 00 (ads00) internal bus ads002 ads001 ads000 selector tap selector adcs00 fr020 fr010 fr000
pd780833y data sheet u15012ej1v0ds 24 5.6 serial interface four serial interface channels are incorporated. serial interface uart0 serial interface sio30, 31 serial interface iic0 (1) serial interface uart0 the serial interface uart0 operates in asynchronous serial interface (uart) mode. asynchronous serial interface (uart) mode this mode enables full-duplex operation wherein one byte of data following the start bit is transmitted and received. the on-chip uart-dedicated baud rate generator enables communication using a wide range of selectable baud rates. in addition, a baud rate can be also defined by dividing the clock input to the asck0 pin. the uart-dedicated baud rate generator can also be used to generate a midi-standard baud rate (31.25 kbps). figure 5-12. block diagram of serial interface uart0 internal bus receive buffer register (rxb0) rxd0/p24 txd0/p25 receive shift register (rx0) pe0 fe0 ove0 asynchronous serial interface status register 0 (asis0) intser0 intst0 baud rate generator f x /2 to f x /2 7 txe0 rxe0 ps01 ps00 cl0 sl0 isrm0 asynchronous serial interface mode register 0 (asim0) intsr0 receive controller (parity check) transmit shift register (txs0) transmit controller (parity addition) p26/asck0
pd780833y data sheet u15012ej1v0ds 25 (2) serial interface sio30 and 31 the serial interfaces sio30 and 31 operate in 3-wire serial i/o mode. 3-wire serial i/o mode (fixed as msb first) this is an 8-bit data transfer mode using three lines: a serial clock line (sck3n), a serial output line (so3n), and a serial input line (si3n). since simultaneous transmit and receive operations are possible in the 3-wire serial i/o mode, the processing time for data transfer is reduced. the first bit of the 8-bit data in the serial transfer is fixed as msb. the 3-wire serial i/o mode is useful for connection to peripheral i/o devices that include a clocked serial interface, display controllers, etc. remark n = 0, 1 figure 5-13. block diagram of serial interface sio30 internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 30 (sio30) si30/p30 so30/p31 sck30/p32 intcsi30 f x /2 3 f x /2 4 f x /2 6 figure 5-14. block diagram of serial interface sio31 internal bus 8 serial clock controller serial clock counter interrupt request signal generator selector serial i/o shift register 31 (sio31) si31/p20 so31/p21 sck31/p22 intcsi31 f x /2 3 f x /2 4 f x /2 6
pd780833y data sheet u15012ej1v0ds 26 (3) serial interface iic0 the serial interface iic0 operates in the i 2 c (inter ic) bus mode (multimaster supported). ? 2 c bus mode (multimaster supported) this is an 8-bit data transfer mode using two lines: a serial clock line (scl0) and a serial data bus line (sda0). this mode complies with the i 2 c bus format, and can output start condition , data , and stop condition during transmission via the serial data bus. this data are automatically detected by hardware during reception. since scl0 and sda0 are open-drain outputs in iic0, pull-up resistors for the serial clock line and the serial data bus line are required. figure 5-15. block diagram of serial interface iic0 internal bus iic status register 0 (iics0) iic control register 0 (iicc0) slave address register 0 (sva0) noise eliminator match signal iic shift register 0 (iic0) so0 latch iice0 d set clear cl01, cl00 sda0/p71 scl0/p72 n-ch open- drain output data hold time correction circuit acknowledge detector wake-up controller acknowledge detector stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic0 f x cld0 iic transfer clock select register 0 (iiccl0) internal bus lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 msts0 ald0 exc0 coi0 trc0 adkd0 std0 spd0 start condition detector dad0 smc0 dfc0 cl01 n-ch open- drain output noise eliminator q cl00 clx0 iic function expansion register 0 (iicx0) 3
pd780833y data sheet u15012ej1v0ds 27 table 5-3. examples of symbols symbol name symbol (example of symbols in normal transmission mode) sof (start of frame) logical state 0 logical state 1 eof (end of frame) break signal 5.7 j1850 (class2) bus controller the pd780833y includes a bus controller compliant with j1850 (class2). the protocol of j1850 (class2) is the variable pulse width modulation (vpw) method. the protocol conforms to the rules stated below. (1) the potential level is changed at each bit. (2) a logical value, 1 or 0, is determined by the potential level and pulse width. (3) a logical value of 0 takes precedence. a message begins with an sof (start of frame) symbol and contains one to 11 bytes of data except in block mode, in which the data length is not limited. data is transmitted serially in descending order of bits, that is, bit 7 is transmitt ed first, and bit 0 is transmitted last. the last bit, bit 0, is followed by the cyclic redundancy check (crc) field. a message is concluded with an eof (end of frame). the break signal is a single pulse. examples of a message and symbols are shown below. figure 5-16. example of message 2 to 11 bytes sof byte 1 crc eof 0011011 0 msb lsb active 200 s 64 s passive 128 s active 64 s active 128 s passive passive > 280 s active > 768 s
pd780833y data sheet u15012ej1v0ds 28 6. interrupt functions a total of 30 interrupt sources are provided, divided into the following three types. non-maskable: 1 maskable: 28 software: 1 table 6-1. interrupt source list (1/2) interrupt default interrupt source internal/ type priority note 1 name trigger external non- intwdt watchdog timer overflow internal 0004h (a) maskable (with watchdog timer mode 1 selected) maskable 0 intwdt watchdog timer overflow (b) (with interval timer mode selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intp7 0014h 9 intser0 uart0 reception error generation internal 0016h (b) 10 intsr0 end of uart0 reception 0018h 11 intst0 end of uart0 transmission 001ah 12 intcsi30 end of sio30 transfer 001ch 13 intcsi31 end of sio31 transfer 001eh 14 intiic0 end of iic0 transfer 0020h 15 intc2 class2 wake-up request, reception completion, 0022h sleep enable, reception error 16 intwtni0 reference time interval signal from watch timer 0024h 17 inttm000 match between tm00 and cr000 (when compare 0026h register is specified). valid edge detection of ti000 pin (when capture register is specified). 18 inttm010 match between tm00 and cr010 (when compare 0028h register is specified). valid edge detection of ti010 pin (when capture register is specified). notes 1. the default priority is the priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest and 27 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively. remark two watchdog timer interrupt sources (intwdt) are available: a non-maskable interrupt and a maskable interrupt (internal), either of which can be selected. vector basic table configuration address type note 2
pd780833y data sheet u15012ej1v0ds 29 table 6-1. interrupt source list (2/2) interrupt default interrupt source internal/ type priority note 1 name trigger external maskable 19 inttm001 match between tm01 and cr001 (when compare internal 002ah (b) register is specified). valid edge detection of ti001 pin (when capture register is specified). 20 inttm011 match between tm01 and cr011 (when compare 002ch register is specified). valid edge detection of ti011 pin (when capture register is specified). 21 intad00 end of a/d converter (ad00) conversion 002eh 22 intad01 end of a/d converter (ad01) conversion 0030h 23 intwtn0 watch timer overflow 0034h 24 intkr port 4 falling edge detection external 0036h (d) 25 inttm50 match between tm50 and cr50 internal 0038h (b) 26 inttm51 match between tm51 and cr51 003ah 27 inttm52 match between tm52 and cr52 003ch software brk brk instruction execution 003eh (e) notes 1. the default priority is the priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest and 27 is the lowest. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1, respectively. remark two watchdog timer interrupt sources (intwdt) are available: a non-maskable interrupt and a maskable interrupt (internal), either of which can be selected. vector basic table configuration address type note 2
pd780833y data sheet u15012ej1v0ds 30 figure 6-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0 to intp7) internal bus priority controller vector table address generator standby release signal interrupt request mk internal bus ie pr isp if priority controller vector table address generator standby release signal interrupt request mk ie pr isp if priority controller vector table address generator external interrupt edge enable register (egp, egn) edge detector standby release signal interrupt request internal bus
pd780833y data sheet u15012ej1v0ds 31 figure 6-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (intkr) (e) software interrupt if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag mk ie pr isp if priority controller vector table address generator falling edge detector internal bus standby release signal interrupt request priority controller vector table address generator internal bus interrupt request
pd780833y data sheet u15012ej1v0ds 32 7. standby functions the following two standby functions are provided to reduce the current consumption. halt mode: the cpu operating clock is stopped. the average current consumption can be reduced by intermittent operation in combination with the normal operating mode. stop mode: the system clock oscillation is stopped. all operations using the system clock are stopped, so that the system operates with ultra-low power consumption. figure 7-1. standby function 8. reset functions the following two reset methods are available. external reset by reset signal input internal reset by watchdog timer loop time detection stop mode (system clock oscillation stopped) system clock operation halt mode (clock supply to cpu is stopped, oscillation maintained) interrupt request halt instruction interrupt request stop instruction
pd780833y data sheet u15012ej1v0ds 33 9. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz note except r = a second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a r add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc mov mov add addc sub subc and or xor cmp inc dec b, c sfr mov mov dbnz mov add addc sub subc and or xor cmp saddr mov dbnz inc dec !addr16 mov psw mov mov push pop [de] ror4 mov [hl] mov rol4 [hl + byte] [hl + b] [hl + c] mov x c mulu divuw
pd780833y data sheet u15012ej1v0ds 34 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw note only when rp = bc, de or hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction compound instruction br call br callf callt br, bc, bnc bz, bnz bt, bf btclr dbnz second operand first operand ax rp sfrp saddrp !addr16 sp #word addw subw cmpw movw movw movw movw ax movw note movw movw movw movw movw xchw rp note sfrp movw saddrp movw !addr16 movw sp movw none incw, decw push, pop second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit sfr.bit saddr.bit psw.bit [hl].bit cy mov1 mov1 mov1 mov1 mov1 bt bf btclr bt bf btclr bt bf btclr bt bf btclr bt bf btclr set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 set1 clr1 not1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1
pd780833y data sheet u15012ej1v0ds 35 parameter symbol conditions ratings unit supply voltage v dd v dd = av dd = av ref ?.3 to +6.5 v av dd av ref av ss ?.3 to +0.3 v input voltage v i1 p00 to p07, p20 to p27, p30 to p32, p34 to p36, ?.3 to v dd + 0.3 v p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 to p87, p90 to p97, c2rx, x1, x2, reset v i2 p33 n-ch open-drain ?.3 to +16 v output voltage v o p00 to p07, p20 to p27, p30 to p36, p40 to p47, ?.3 to v dd + 0.3 v p50 to p57, p64 to p67, p70 to p75, p80 to p87, p90 to p97, c2tx analog input voltage v an ani00 to ani70 analog input pin av ss ?0.3 to av ref + 0.3 v ani01 to ani71 and ?.3 to v dd + 0.3 output current, high i oh per pin for p00 to p07, p20 to p27, p30 to p32, ?0 ma p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70, p73 to p75, p80 to p87, p90 to p97, c2tx total for all pins 30 ma output current, low note i ol per pin for p00 to p07, p20 to p27, peak value 20 ma p30 to p32, p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, rms value 10 ma p80 to p87, p90 to p97, c2tx p33 pin peak value 30 ma rms value 15 ma total for all pins peak value 100 ma rms value 60 ma operating ambient t a ?0 to +85 c temperature storage temperature t stg ?5 to +150 c 10. electrical specifications absolute maximum ratings (t a = 25 c) note the rms value should be calculated as follows: [rms value] = [peak value] duty caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
pd780833y data sheet u15012ej1v0ds 36 resonator recommended circuit parameter conditions min. typ. max. unit ceramic oscillation 4.0 8.4 mhz resonator frequency (f x ) note 1 oscillation 4 ms stabilization time note 2 crystal oscillation 4.0 4.2 mhz resonator frequency (f x ) note 1 oscillation 10 ms stabilization time note 2 notes 1. indicates only oscillator characteristics. 2. time required to stabilize oscillation after reset or stop mode release. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) c1 x2 x1 test c2 r1 x1 test x2 c2 c1 r1
pd780833y data sheet u15012ej1v0ds 37 capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz 15 pf unmeasured pins returned to 0 v. output capacitance c out f = 1 mhz 15 pf unmeasured pins returned to 0 v. i/o capacitance c io f = 1 mhz p00 to p07, p20 to p27, p30 to p32, 15 pf unmeasured pins p34 to p36, p40 to p47, p50 to p57, returned to 0 v. p64 to p67, p70 to p75, p80 to p87, p90 to p97 p33 20 pf remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
pd780833y data sheet u15012ej1v0ds 38 dc characteristics (t a = ?0 to +85 c, v dd = av dd = av ref = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 p21, p25, p31, p34, p40 to p47, p64 to p67, 0.7v dd v dd v p70 to p73, p80 to p87, p90 to p97 v ih2 p00 to p07, p20, p22 to p24, p26, p27, p30, p32, 0.8v dd v dd v p35, p36, p74, p75, reset v ih3 p50 to p57 2.3 v dd v v ih4 p33 (n-ch open drain) 0.7v dd 15 v v ih5 x1, x2 v dd 0.5 v dd v v ih6 c2rx 0.8v dd v dd + 0.2 v input voltage, low v il1 p21, p25, p31, p34, p40 to p47, p64 to p67, 0 0.3v dd v p70 to p73, p80 to p87, p90 to p97 v il2 p00 to p07, p20, p22 to p24, p26, p27, p30, p32, 0 0.2v dd v p35, p36, p74, p75, c2rx, reset v il3 p50 to p57 0 0.75 v v il4 p33 (n-ch open drain) 0 0.3v dd v v il5 x1, x2 0 0.4 v output voltage, high v oh1 i oh = 1 ma p00 to p07, p20 to p27, p30 to p32, v dd 1.0 v dd v p34 to p36, p40 to p47, p50 to p57, v oh2 i oh = 100 a p64 to p67, p70, p73 to p75, v dd 0.5 v dd v p80 to p87, p90 to p97, c2tx output voltage, low v ol1 i ol = 15 ma p33 0.4 2.0 v v ol2 i ol = 1.6 ma p71, p72 0.4 v v ol3 i ol = 1 ma p00 to p07, p20 to p27, p30 to p32, 1.0 v p34 to p36, p40 to p47, p50 to p57, v ol4 i ol = 500 a p64 to p67, p70, p73 to p75, 0.5 v p80 to p87, p90 to p97, c2tx input leakage i lih1 v in = v dd p00 to p07, p20 to p27, p30 to p32, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 to p87, p90 to p97, c2rx, reset i lih2 x1 20 a i lih3 v in = 15 v p33 80 a input leakage i lil1 v in = 0 v p00 to p07, p20 to p27, p30 to p32, 3 a current, low p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 to p87, p90 to p97, c2rx, reset i lil2 x1 20 a i lil3 p33 3 note a note a low-level input leakage current of 200 a (max.) flows through p33 for only 1 clock after executing a read instruction to port 33 (p33). other than that period, 3 a (max.) flows. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
pd780833y data sheet u15012ej1v0ds 39 parameter symbol conditions min. typ. max. unit output leakage i loh v out = v dd p00 to p07, p20 to p27, p30 to p32, 3 a current, high p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70, p73 to p75, p80 to p87, p90 to p97, c2tx output leakage i lol v out = 0 v p00 to p07, p20 to p27, p30 to p36, 3 a current, low p40 to p47, p50 to p57, p64 to p67, p70 to p75, p80 to p87, p90 to p97, c2tx software pull-up r 1 v in = 0 v p00 to p07, p20 to p27, p30 to p32, 15 30 90 k ? resistance p34 to p36, p40 to p47, p50 to p57, p64 to p67, p70, p73 to p75 supply i dd1 4.19 mhz crystal oscillation operating mode note 2 49ma current note 1 8.38 mhz crystal oscillation operating mode note 2 818ma i dd2 4.19 mhz crystal oscillation halt mode note 3 400 700 a 8.38 mhz crystal oscillation halt mode note 3 700 1200 a i dd3 stop mode 0.1 30 a dc characteristics (t a = ?0 to +85 c, v dd = av dd = av ref = 4.5 to 5.5 v) notes 1. refers to total current flowing to the internal power supplies (v dd1 and v ss1 ). the current flowing to av ref , av dd , and the ports (on-chip pull-up resistors) is not included. 2. high-speed mode operation (when the processor clock control register (pcc) is set to 00h) 3. low-speed mode operation (when the processor clock control register (pcc) is set to 04h). the wtn0 operating current and class2 signal receive wait status operating current (when bit 5 (c2sc1) and bit 4 (c2sc0) of the class 2 clock selection register (c2clk) are set to 00b) are included. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
pd780833y data sheet u15012ej1v0ds 40 parameter symbol conditions min. typ. max. unit cycle time t cy when using ceramic resonator 0.238 8 s (minimum instruction execution time) when using crystal resonator 0.476 8 s ti000, ti010, t tih0 2/f sam + 0.1 note s ti001, ti011 input t til0 high-/low-level width ti50, ti51, ti52 input f ti5 0 2.5 mhz frequency ti50, ti51, ti52 input t tih5 160 ns high-/low-level width t til5 interrupt request input t inth intp0 to intp7, p40 to p47 10 s high-/low-level width t intl reset t rsl 10 s low-level width ac characteristics (1) basic operation (t a = 40 to +85 c, v dd = 4.5 to 5.5 v) note selection of f sam = f x , f x /4, f x /64 is available with bits 0 and 1 (prm0n0, prm0n1) of prescaler mode register 0n (prm0n). however, if the ti00n valid edge is selected as the count clock, the value becomes f sam = f x /8 (n = 0, 1).
pd780833y data sheet u15012ej1v0ds 41 (2) serial interface (t a = 40 to +85 c, v dd = 4.5 to 5.5 v) (a) sio3 3-wire serial i/o mode (internal clock output): sio30, sio31 parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy1 952 ns sck3 high-/low-level t kh1 , t kl1 t kcy1 /2 50 ns width si3 setup time t sik1 100 ns (to sck3 ) si3 hold time t ksi1 400 ns (from sck3 ) delay time from sck3 t kso1 c = 100 pf note 300 ns to so3 output parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy2 800 ns sck3 high-/low-level t kh2 , t kl2 400 ns width si3 setup time t sik2 100 ns (to sck3 ) si3 hold time t ksi2 400 ns (from sck3 ) delay time from sck3 t kso2 c = 100 pf note 300 ns to so3 output note c is the load capacitance of the so3 output line. note c is the load capacitance of the sck3 and so3 output lines. (b) sio3 3-wire serial i/o mode (external clock input): sio30, sio31 (c) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 131250 bps parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy3 800 ns asck0 high-/low-level t kh3 , t kl3 400 ns width transfer rate 39063 bps (d) uart0 (external clock input)
pd780833y data sheet u15012ej1v0ds 42 (e) i 2 c bus mode parameter symbol standard mode high-speed mode unit min. max. min. max. scl0 clock frequency f scl 0 100 0 400 khz bus free time t buf 4.7 1.3 s (between stop and start condition) hold time note 1 t hd:sta 4.0 0.6 s scl0 clock low-level width t low 4.7 1.3 s scl0 clock high-level width t high 4.0 0.6 s start/restart condition setup time t su:sta 4.7 0.6 s data hold time cbus compatible master t hd:dat 5.0 s i 2 c bus 0 note 2 0 note 2 0.9 note 3 s data setup time t su:dat 250 100 note 4 ns sda0 and scl0 signal rise time t r 1000 300 ns sda0 and scl0 signal fall time t f 300 300 ns stop condition setup time t su:sto 4.0 0.6 s capacitive load per bus line cb 400 400 pf notes 1. on start condition output, the first clock pulse is generated after this hold period. 2. to fill the undefined area of the scl0 falling edge, it is necessary for the device to provide at least 300 ns of hold time internally for the sda0 signal (on v ihmin. of scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only the maximum data hold time t hd:dat needs to be satisfied. 4. the high-speed mode i 2 c bus is available in the standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. if the device does not extend the scl0 signal low state hold time t su:dat 250 ns if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by standard mode i 2 c bus specification).
pd780833y data sheet u15012ej1v0ds 43 (3) class2 (t a = 40 to +85 c, v dd = 4.5 to 5.5 v) (a) internal clock count limit parameter symbol conditions min. typ. max. unit internal clock cycle time t cclk 467 510 ns (b) in normal mode parameter symbol conditions min. typ. max. unit rise time propagation delay t pdr 62t cclk s (from c2tx to c2rx ) fall time propagation delay t pdf 62t cclk s (from c2tx to c2rx ) (c) in quadruple-speed mode parameter symbol conditions min. typ. max. unit rise time propagation delay t pdrx 8t cclk s (from c2tx to c2rx ) fall time propagation delay t pdfx 8t cclk s (from c2tx to c2rx ) (d) transmission/reception pulse width (in normal mode) symbol t xmin t xnom t xmax t rmin t rmax unit when passive: 0, active: 1 60 64 68 37 91 or below s when passive: 1, active: 0 122 128 134 100 157 or below s when active is sof 193 200 207 170 230 s when passive is eof 271 280 289 249 320 or below s idle point 320 or above 8t cclk s when active is break 768 249 or above s (e) transmission/reception pulse width (in quadruple-speed mode) symbol t xmin t xnom t xmax t rmin t rmax unit when passive: 0, active: 1 15 16 17 10 22 s when passive: 1, active: 0 30 32 34 25 39 s when active is sof 48 50 52 43 57 s when passive is eof 68 70 72 63 80 s idle point 80 8t cclk s when passive: 0, active: 1 768 63 s
pd780833y data sheet u15012ej1v0ds 44 ac timing test points (excluding x1 input) clock timing ti timing 0.8v dd 0.2v dd 0.8v dd 0.2v dd test points t xl t xh 1/f x v ih5 (min.) v il5 (max.) x1 input 1/f ti5 t tih5 t til5 ti50, ti51, ti52 ti000, ti010, ti001, ti011 t til0 t tih0 interrupt request input timing reset input timing intp0 to intp7 t intl t inth t rsl reset
pd780833y data sheet u15012ej1v0ds 45 serial transfer timing 3-wire serial i/o mode: uart mode (external clock input): i 2 c bus mode: si30, si31 so30, so31 t kcyn t kln t khn t sikn t ksin input data t kson output data sck30, sck31 t kcy3 t kh3 t kl3 asck0 scl0 sda0 t hd:sta t buf t hd:dat t f t su:dat t su:sta t sp t su : sto t r stop condition start condition stop condition restart condition t high t hd:sta t low
pd780833y data sheet u15012ej1v0ds 46 class2 propagation waveform (example of short pulse width) remarks 1. the meanings of the symbols in the above figure are as follows: t pdr : rise time propagation delay in normal mode of the class2 transceiver t pdf : fall time propagation delay in normal mode of the class2 transceiver t pdrx : rise time propagation delay in quadruple-speed mode of the class2 transceiver t pdfx : fall time propagation delay in quadruple-speed mode of the class2 transceiver 2. the values of t pdr , t pdf , t pdrx , and t pdfx , can be specified using the class 2 rise time propagation delay correction register (c2pdr) and class 2 fall time propagation delay correction register (c2pdf). t pdr c2tx c2rx 64 s t pdf 64 s 64 s t pdf t pdr 64 s t pdr t pdrx c2tx c2rx 16 s t pdfx 16 s 16 s t pdfx t pdrx 16 s t pdrx
pd780833y data sheet u15012ej1v0ds 47 a/d converter characteristics (t a = 40 to +85 c, v dd = av dd = av ref = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit overall error note 0.6 %fsr conversion time t conv 14 100 s analog input voltage v ian av ss av ref v av ref resistance r airef 9.5 15 37 k ? note excludes quantization error ( 0.2%fsr). it is indicated as a ratio to the full-scale value. data memory stop mode low supply voltage data retention characteristics (t a = 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power v dddr 2.0 5.5 v supply voltage data retention i dddr v dddr = 2.0 v 0.1 10 a power supply current release signal set time t srel 0 s oscillation stabilization wait time t wait release by reset 2 17 /f x ms release by interrupt request note ms note selection of 2 12 /f x , 2 14 /f x , 2 15 /f x , 2 16 /f x , and 2 17 /f x is possible with bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). data retention timing (stop mode release by reset) t srel t wait v dd reset stop mode data retention mode internal reset operation halt mode operating mode v dddr stop instruction execution
pd780833y data sheet u15012ej1v0ds 48 data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
pd780833y data sheet u15012ej1v0ds 49 11. package drawing 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
pd780833y data sheet u15012ej1v0ds 50 12. recommended soldering conditions for the solder mounting method and soldering conditions of the pd780833y, contact an nec sales representative.
pd780833y data sheet u15012ej1v0ds 51 appendix a. development tools the following development tools are available for system development using the pd780833y. also refer to (5) cautions on using development tools . (1) language processing software ra78k0 assembler package common to 78k/0 series cc78k0 c compiler package common to 78k/0 series df780833 device file for pd780833y subseries cc78k0-l c compiler library source file common to 78k/0 series (2) flash memory writing tools flashpro ii flash programmer dedicated to on-chip flash memory microcontrollers (part no.: fl-pr2) flashpro iii (part no.: fl-pr3, pg-fp3) fa-80gc adapter for flash memory writing used by connecting the flashpro ii or flashpro iii. this is for 80-pin plastic qfp (gc-8bt type). (3) debugging tool when using in-circuit emulator ie-78k0-ns ie-78k0-ns in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-cd-if-a pc card and interface cable when using notebook pc as host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when using ibm pc/at tm compatible as host machine (isa bus supported) ie-70000-pci-if-a adapter necessary when using on-chip pci bus pc as host machine ie-780833-ns-em4 emulation board to emulate pd780833y subseries ie-78k0-ns-p02 i/o board necessary when using ie-780833-ns-em4 np-80gc emulation probe for 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 conversion socket to connect target system on which an 80-pin plastic qfp (gc-8bt type) can be mounted and np-80gc id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df780833 device file for pd780833y subseries
pd780833y data sheet u15012ej1v0ds 52 when using in-circuit emulator ie-78001-r-a ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c interface adapter when using pc-9800 series as host machine (excluding notebook pcs) (c bus supported) ie-70000-pc-if-c interface adapter when using ibm pc/at compatible as host machine (isa bus supported) ie-70000-pci-if-a adapter necessary when using on-chip pci bus pc as host machine ie-78000-r-sv3 interface adapter and cable when using ews as host machine ie-780833-ns-em4 emulation board to emulate pd780833y subseries ie-78k0-ns-p02 i/o board necessary when using ie-780833-ns-em4 ie-78k0-r-ex1 emulation probe conversion board necessary to use ie-780833-ns-em4 + ie-78k0-ns-p02 on ie- 78001-r-a ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 conversion socket to connect target system board manufactured for 80-pin plastic qfp (gc-8bt type) and ep-78230gc-r id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780833 device file for pd780833y subseries (4) real-time os rx78k0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
pd780833y data sheet u15012ej1v0ds 53 host machine pc ews [os] pc-9800 series [japanese windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatible sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k0 note cc78k0 note id78k0-ns id78k0 ? sm78k0 rx78k0 note mx78k0 note note dos-based software (5) cautions on using development tools the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780833. the cc78k0 and rx78k0 are used in combination with the ra78k0 and the df780833. the fl-pr2, fl-pr3, fa-80gc, and np-80gc are products of naito densei machida mfg. co., ltd. (+81- 44-822-3813). for third-party development tools, see the single-chip microcontroller development tool selection guide (u11069e) . the host machines and oss supporting each software are as follows.
pd780833y data sheet u15012ej1v0ds 54 conversion socket (ev-9200gc-80) drawing and footprints figure a-1. ev-9200gc-80 drawing (for reference only) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g1e item millimeters inches a b c d e f g h i j k l m n o p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059
pd780833y data sheet u15012ej1v0ds 55 figure a-2. ev-9200gc-80 footprints (for reference only) a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 +0.001 ?.002 +0.003 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 +0.001 ?.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution
pd780833y data sheet u15012ej1v0ds 56 appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd780833y subseries user? manual u13892e pd780833y data sheet this document pd78f0833y data sheet u15013e 78k/0 series user? manual instructions u12326e documents related to development tools (user? manuals) document name document no. ra78k0 assembler package operation u11802e language u11801e structured assembly language u11789e cc78k0 c compiler operation u11517e language u11518e ie-78k0-ns u13731e ie-78k0-r-ex1 to be prepared ie-780833-ns-em4 to be prepared sm78k0s, sm78k0 system simulator windows based operation u14611e sm78k series system simulator external part user open to be prepared ver. 2.10 or later interface specifications id78k0-ns integrated debugger ver. 2.00 or later windows based operation u14379e id78k0 integrated debugger windows based guide u11649e reference u11539e caution the related documents listed above are subject to change without notice. be sure to read the latest version of each document before designing.
pd780833y data sheet u15012ej1v0ds 57 documents related to embedded software (user s manuals) document name document no. 78k/0 series real-time os fundamentals u11537e installation u11536e 78k/0 series os mx78k0 fundamental u12257e other related documents document name document no. semiconductor selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to read the latest version of each document before designing.
pd780833y data sheet u15012ej1v0ds 58 purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip and iebus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation.
pd780833y data sheet u15012ej1v0ds 59 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
pd780833y m8e 00. 4 the information in this document is current as of october, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ? the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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